Partial runtime reconfiguration of FPGA, applications and a fault emulation case study
Authors
U.Legat, A.Biasizzo, F.Novak
Publication
International Review on Computers and Software (IRECOS), 2009
Abstract
The paper surveys the basic principles of partial runtime reconfiguration of FPGA and comments on their possible applications in practice. The dynamic partial reconfiguration of FPGA is a process of reconfiguring a part of FPGA logic, while the rest of the logic is unaffected by the configuration. Three different successful examples of reconfigurable applications are presented. The paper also presents a fault emulation case study. By using partial runtime reconfiguration the fault injection time is significantly reduced. Fault is injected during run-time using an embedded microprocessor and only the resource affected by the fault is reconfigured. The approach is demonstrated using a hardware implementation of Advanced Encryption Standard (AES) algorithm. This work has been done as a preliminary feasibility study for concurrent test solutions in mission critical applications.
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