On-line error detection and BIST of a 32-bit FPGA hardware AES implementation
Authors
U.Legat, A.Biasizzo, F.Novak
Publication
Microprocessors and microsystems, 2011, 35(4): 405-416
Abstract
This paper presents low cost on-line error detection architecture for a 32-bit hardware implementation of the AES and proposes a novel BIST method. Our compact implementation of AES is optimized for FPGA based embedded applications since it is tuned to specific FPGA logic resources. It was designed for a gaming system application in which a high level of security and reliability is required. In order to provide more reliable operation and reduce the possibility of suffering from fault-based side channel attacks we developed the on-line error detection based on parity codes. Parity prediction is implemented in AES encryption, decryption and key expansion process. Developed solution has been upgraded to an efficient BIST with high fault coverage and low hardware overhead.
BIBTEX copied to Clipboard