Stochastic Approach to Test Pattern Generator Design
Authors
G. Papa, T. Garbolino
Publication
InTech, 2011, 75-94
Abstract
The fast growing complexity of modern integrated circuits and rapid changes in technology pose a number of challenges in testing of electronic products. With the introduction of surface mounted devices, small pitch packaging becomes prevalent, which makes the access to the test points on a board either impossible or at least very costly. Traditional in-circuit test techniques that utilize a bed-of-nails to make contact to individual leads on a printed circuit board have become inadequate. This forced the development of a boundary-scan approach that is already widely adopted in practice. But, a limited number of input/output pins represents a bottleneck in testing of complex embedded cores where transfers of large amounts of test patterns and test results between the automatic test equipment and the unit-under-test are required. However, the implementation of a built-in self-test of the unit-under-test with on-chip test pattern generation and on-chip output response analysis logic presents an efficient solution. Then the communication with external automatic test equipment is reduced to test initiation and transfer of test results.
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