Application of SRAM based FPGAs in mission critical requires error mitigation and recovery techniques to protect them from the errors caused by high energy radiation also known as Single Event Upsets (SEU).
Modular redundancy and runtime partial reconfiguration are commonly employed techniques. Reported solutions feature different trade-off of area-overhead and fault latency. In this paper we propose a low area-overhead SEU recovery mechanism and describe its application in different self-recoverable architectures, which are experimentally evaluated using specially designed fault emulation environment. The environment enables the user to inject faults in selected locations of the configuration memory and experimentally evaluate the reliability of developed solutions.