A multi-alphabet arithmetic coding hardware implementation for small FPGA devices
Authors
A. Biasizzo, F. Novak, P. Korošec
Publication
Journal of Electrical Engineering - Elektrotechnicky Casopis, 2013, 64(1): 44-49
Abstract
Arithmetic coding is a lossless compression algorithm with variable-length source coding. It is more flexible and efficient than the well-known Huffman coding. In this paper we present a non-adaptive FPGA implementation of a multi-alphabet arithmetic coding with separated statistical model of the data source. The alphabet of the data source is a 256-symbol ASCII character set and does not include the special end-of-file symbol. No context switching is used in the proposed design which gives maximal throughput without pipelining. We have synthesized the design for Xilinx FPGA devices and used their built-in hardware resources.
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