On-line Testing and Recovery of Systems with Dynamic Partial Reconfiguration
Authors
A. Biasizzo
Publication
Informacije MIDEM, 2013, 43(4): 259 – 266
Abstract
The FPGA devices are increasingly being used in mission critical systems like security systems, banking systems, and avionics. The errors induced by high-energy radation, also known as Single Event Upsets (SEUs), corrupt the configuration memory of the FPGA device and are a major concern for the system reliability and dependability. For this, error mitigation techniques like triple module redundancy and ECC codes are commonl;y employed techniques. However error mitigation techniques do not recover the system. The fault-free system can be recovered using reconfiguration of the FPGA device. Existing (previous) recovery methods employ processor cores as a reconfiguration controller consuming notable amount of device resources and introducing additional error detection and recovery latency. In tes paper a low area overhead error recovery mechanism for SRAM based FPGA systems is presented. The error recovery mechanism is implemented as a state machine and is further improved by employing complementary error mitigation techniques like the triple modular redundancy. The reliability of the developed solution was experimentally evaluated by fault emulation environment.
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