Uroš Legat

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Uroš Legat, Ph.D.
uros.legat@ijs.si
About
Activities
Academic
Research
Publications
Journal articles
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On line self recovery of embedded multi-core SOC on FPGA using dynamic partial reconfiguration
SEU recovery mechanism for SRAM based FPGAs
On-line error detection and BIST of a 32-bit FPGA hardware AES implementation
Partial runtime reconfiguration of FPGA, applications and a fault emulation case study
Conference papers
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Hardware implementation of locking mechanism for IEEE Std 1149.1
Books & Chapters
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Projects
Research
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Applied
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