In this paper an approach for the generation of deterministic test pattern generator logic composed of D-type and T-type flip-flops is described. The approach employs a genetic algorithm to find an acceptable practical solution in a large space of possible implementations. In contrast to conventional approaches our genetic algorithm approach reduces the gate count of built-in self-test structure by concurrent optimization of multiple parameters that influence the final solution. Results of experiments with combinational benchmarks demonstrate the efficiency of the proposed evolutionary approach.