Synchronous dataflow-based architecture
J. Šilc, B. Robič
Microprocessing and Microprogramming, 1989, 27(1-5): 315-322
Many specialized computations can be directly represented by means of acyclic dataflow programs. Moreover, for many programs containing loop constructs, all the repetitively executed subgraphs can be unravelled in advance. For the class of all such acyclicaly representable dataflow programs, we propose a parallel architecture which supports synchronous dataflow computing. The advantage of such computing over conventional dataflow is that more efficient runtime code can be generated because instructions can be scheduled at a compile time rather than at runtime. Two heuristic methods are developed to transform a dataflow graph into an allocated dataflow graph, so that either processor requirements or time duration of programs are minimized. Besides processor and time minimization an important advantage of the proposed architecture is also reduced amount of control information which is transmitted during execution along with the data. We present simulation results which justify the use of the proposed architecture for the mentioned class of dataflow programs.
BIBTEX copied to Clipboard