Jure Vreča

Journal articlesshow recent

Hardware–Software Co-Design of an Audio Feature Extraction Pipeline for Machine Learning Applications, (2024)

Conference papersshow all

Towards Deploying Highly Quantized Neural Networks on FPGA Using Chisel, DSD
A Configurable Mixed-Precision Convolution Processing Unit Generator in Chisel, DDECS

Books & Chaptersshow recent

Hardware Acceleration of the YOLO Convolutional Neural Network on a Field-Programmable Gate Array

Iva Ivanov, Jure Vreca, Anton Biasizzo
Proc. 57th International Conference on Microelectronics, Devices and Materials
, T.Rojac, M.Otoničar, I. Šorli (Eds.)
Maribor: 14.-16. September 2022
pages: 56-61

abstract:
A case study of a power-efficient and real-time object detection system is presented. We targeted the YOLOv4 convolutional neural network and introduced slight modifications in its architecture, in order to make it compatible with the targeted hardware accelerator platform. The obtained results demonstrate the benefits of the FPGAs over CPUs and GPUs for time and power consumption sensitive applications. The detection accuracy of the quantized model had dropped by 5% to 14%, depending on the input image size of the YOLOv4 neural network. However, in terms of data throughput, the FPGA-based implementation of the YOLOv4 neural network outperforms the CPU implementation by 284 times, as the CPU does not have the hardware structures necessary to parallelize the processing, hence the processing of deep neural networks is serial and slower compared to FPGA and GPU solutions. In comparison to the FPGA implementation, the GPU implementation achieved 3 times higher processing throughput while consuming 5.4 times the power.